An Evolution of FM Tuner Architectures
By Lawrence Der, Ph.D. Silicon Laboratories Inc.
During the past decade, there have been considerable advances in radio frequency (RF) communication circuit design. These advances stem from new RF architectures that were once considered impossible because of low integration, high power consumption and poor process technology. In addition, the availability of high-performance, dense sub-micron CMOS technology has dramatically changed the approach to designing RF communication circuits by enabling digital techniques. Designers have applied these techniques to many wireless communication standards, such as GPS, WLAN and cellular phone standards, enabling robust, highly-integrated chipset solutions that improve overall system performance and reliability. The advantages of integrating external components and RF circuits with the digital baseband are to reduce the bill-of-materials (BOM), decrease required board space, simplify the board level design of the application, and improve manufacturability.
Improvements in manufacturability come from the complete integration of the system on to the chip. This reduces the number of external components that need testing. Examples of integration are readily found in many modern communication applications, but until recently the frequency modulation (FM) radio broadcast standard has lacked technology improvements. Even in today’s digital era, many portable FM radios still contain over 15 external components. Radio manufacturers base their designs on old analog technology that was designed with expensive, low-integration bipolar or Bi-CMOS processes.
Despite continuous growth in the FM tuner-related products market, FM tuner radio architecture has remained virtually unchanged. The recent introduction of a fully-integrated 100 percent CMOS digital low-IF architecture represents the first significant evolution of FM tuner radio architecture in 10 years. Previously, designers have used several RF architectures for FM tuners, each offering its own advantages and disadvantages. For the purpose of discussion, we will examine traditional FM transmitter and FM receiver architectures to understand the general architecture of FM systems. We will also highlight multiple evolutions of FM tuners leading to the new digital low-IF architecture for FM receivers. In addition, we will explain how this architecture enables high-performance and complete integration of an FM tuner with only one external bypass capacitor.
Figure 1. Block Diagram of (a) FM Transmitter and (b) FM Receiver.
Figure 1 shows a traditional FM transmitter and receiver. The FM transmitter first passes the left and right audio signals through a pre-emphasis filter. The transmitter then combines the signals with the Radio Data Systems (RDS) data to generate the multiplex (MPX) message signal m(t). Next, the transmitter modulates the frequency of the message signal and passes it to an RF transmitter, where it is upconverted to radio frequencies generating the output, xFM(t) Designers can use a voltage-controlled oscillator (VCO) to implement the FM modulator and RF transmitter functions. Conceptually, this direct method of FM modulation will work. In practice, however, designers generally use a phase-locked loop (PLL) to stabilize the carrier frequency from frequency drifts and a power amplifier to drive the antenna.
The FM receiver uses an RF receiver to downconvert the RF signal xFM(t) to baseband. Ideally, the FM demodulator recovers the original message by inverting the modulation process. The receiver then applies the message signal m(t) to the MPX decoder to separate the audio signals and the RDS data. The receiver passes the left and right audio signals through a de-emphasis block to compensate for the linear distortion introduced by the pre-emphasis filter. The cascade action of the pre-emphasis and de-emphasis filters does not affect the left and right signals, but it can substantially attenuate high-frequency noise and interference, theoretically giving a signal-to-noise ratio (SNR) improvement of approximately 13 dB [1, 2].
It is primarily the RF receiver and FM demodulator blocks that determine the performance of an FM tuner. The most basic FM demodulator architecture is a frequency discriminator consisting of a time domain differentiator and an envelope detector. With this type of demodulator, the differentiator converts an FM signal, where the information is contained in the phase, to an AM signal, where the information is contained in the amplitude. The envelope detector then recovers the information from the amplitude. However, amplitude variations from the FM carrier can corrupt the demodulated output of a frequency discriminator. Therefore, an amplitude limiter typically precedes a frequency discriminator to remove the amplitude variations from the carrier. Other common types of FM frequency discriminators are the Foster-Seeley discriminator and the ratio detector [1, 2]. Most early manufacturers designed FM demodulators with frequency discriminators using discrete components such as transformers, transistors, diodes, resistors and capacitors. Today, most designs use integrated circuit solutions.
Figure 2. Generic Block Diagram of a PLL and its Linear Model.
A popular modern FM demodulator topology is the PLL. Figure 2 shows a generic block diagram of a PLL and its linear model. PD is the phase detector, KPD is the phase detector gain, HLF(s) is the loop filter transfer function, and KVCO/s is the VCO transfer function. A PLL is a negative feedback system that locks the phase of the feedback signal, xVCO(t), to the input signal, xFM(t) . An FM signal, xFM(t), is given by the following equation:
Ac is the amplitude of the carrier, fc is the carrier frequency; KVCO is a voltage to frequency conversion constant, and m(t) is the information or message signal. When the loop is locked, the phase error, fe, is constant. The feedback signal xVCO(t) is expressed by the following equation:
Since is constant when the loop is locked, the control voltage to the VCO will be equal to m(t). Intuitively, the negative feedback action of the PLL will force the frequency of the VCO to equal the frequency of the input signal. It does this by adjusting the control voltage of the VCO so that the phase error remains constant. If we remove the message signal from xFM(t), the VCO frequency will lock on to and oscillate at the carrier center frequency, fc. When m(t) is present, xFM(t) will deviate from the center frequency, and, if the loop is locked, the PLL will vary the control voltage of the VCO to track the frequency deviations of xFM(t). Since the output frequency of the VCO is directly proportional to the VCO control voltage ( Δfout=KvcoΔVcontrol ) and the frequency deviation of xFM(t) is directly proportional to the message signal ( Δf= Kvco m(t)), the VCO control voltage will be equal to the message signal, m(t).
Engineers frequently use PLLs as FM demodulators because they can be designed to have lower FM thresholds compared to frequency discriminator demodulators [1,4]. PLLs, frequency-locked loops (FLLs), and frequency demodulators with feedback (FMFBs) are related, and all have the ability to extend the threshold of an FM demodulator . Other FM demodulator architectures exist, but designers most commonly implement these demodulators in integrated circuits with analog and digital techniques.
Figure 3. Simplified Block Diagram of the RF Front End of an FM Tuner.
The radio environment of an FM tuner consists of its desired signal band (88 MHz to 108 MHz in the USA and Europe and 76 to 90 MHz in Japan). It also includes all other signals that pass within the bandwidth of the tuner. Figure 3 shows a simplified block diagram of the RF front-end of an FM tuner. The RF band-pass filter (BPF) does not attenuate channels at the band edges. Therefore, it is typically designed to be slightly wider than the entire FM band. However, high-performance FM tuners employ an RF tracking filter with a much tighter bandwidth to attenuate both out-of-band and in-band interference due to strong FM channels. Most low-cost FM receivers do not use an RF tracking filter because it requires a variable BPF and a control mechanism to vary the filter’s center frequency. Therefore, one of the key requirements of the RF receiver is to handle interference from both out-of-band and in–band signals; others include providing channel selection and amplifying the small RF signals without significantly degrading the signal-to-noise ratio (SNR) of the message signal.
Figure 4. FM Superheterodyne Receiver.
Until the late 1990s, nearly all commercial FM radio receivers had been designed with some form of a superheterodyne receiver. Figure 4 shows a block diagram of a superheterodyne receiver. The superheterodyne receiver translates the FM signal to one or more intermediate frequencies (IF) before FM demodulation. This block diagram shows a superheterodyne receiver with two IFs. The RF BPF is a pre-select filter designed to pass the FM band and attenuate out-of-band interference. Designers add a low-noise amplifier (LNA) after the RF BPF, which attenuates the noise from subsequent stages with its gain, improving the sensitivity of the receiver. Since a mixer identically downconverts signals with frequency offsets equal to the IF above and below the LO frequency, the receiver requires an image-reject BPF to select the desired signal and reject the image. The IF band-pass filters, IF1 BPF and IF2 BPF, are fixed-frequency filters that provide channel selection. The limiter removes amplitude variations from the downconverted signal before it is applied to the FM demodulator. The IF sections of the receiver are generally at a lower frequency than the RF, allowing designers to easily implement gain and filtering with lower power dissipation.
The superheterodyne architecture allows distribution of its gains and filtering across different frequency ranges, providing good noise and interference performance without high-Q filters. However, it also requires many discrete external components, including the RF, image and IF band-pass filters, and the PLL VCOs and loop filter, making it large and expensive [3, 5].
Analog Low IF Receiver
Figure 5. Analog Low-IF Receiver.
The analog low IF architecture is similar to a superheterodyne architecture with one IF stage. The key difference is that the RF PLL and mixer are designed with quadrature signals, allowing on-chip image cancellation. The image frequency is located 2xIF away from the desired signal. Therefore, if the IF signal frequency is low, the image is relatively close to the desired signal, mandating a sharp high-Q image reject filter. However, with a quadrature mixer, designers can attenuate the image using cancellation techniques [3, 5, 6], even with low intermediate frequencies. After image cancellation is performed, channel selection is provided by the IF band-pass filter. Again, amplification (limiting) and channel selectivity are much easier to accomplish at low intermediate frequencies compared to higher IFs or at the RF. The main advantage of the analog low IF receiver is it needs fewer external components. In fact, none are needed if engineers can implement RF and IF band-pass filters on-chip along with the RF PLL. The main drawback is the performance relies on analog components, which are subject to process, voltage and temperature variations. These variations typically limit the image cancellation to about 25 to 30 dB, so the image signal can be quite large depending on the choice of IF. A large image can interfere with the desired signal, and it can be heard at the audio output of the FM tuner at two different LO frequencies. In addition, sharp IF channel filters require a large amount of capacitance and a considerable amount of chip area. A pure analog approach typically limits the adjacent channel selectivity to about 35 to 40 dB, leading to poor interference performance. The system can overload or generate intermod distortion products more easily with larger interference signals feeding through to the FM demodulator.
Digital Low-IF Receiver
Figure 6. Digital Low-IF Receiver Block Diagram.
Figure 6 shows a block diagram of a digital low-IF receiver. The digital low-IF architecture is a mixed-signal architecture that uses an analog-to-digital converter (ADC) to convert the in (I) phase and quadrature (Q) phase IF signals to digital IF signals. The ADC outputs are subsequently downconverted to baseband with a digital quadrature mixer. This architecture has the integration advantage of the analog low-IF architecture with the repeatability and reliability of digital circuit implementations. Engineers can achieve large image rejection with the combination of analog and digital circuits because the digital circuits match perfectly and can be calibrated to remove analog imperfections. Another advantage is the IF low-pass filters do not need to provide complete channel filtering and, in many cases, only provide enough filtering to reduce the alternate channel interferers and provide anti-aliasing filtering for the ADCs. Engineers have implemented channel filtering in the digital domain to achieve sharp filter roll-off and attenuation while minimizing silicon area and utilizing the advantages of high-density sub-micron CMOS. The only major drawback with the digital low-IF architecture is that it requires high-performance ADCs . The actual requirements of the ADCs depend on the intermediate frequency, the amount of interference filtering before the ADC and the dynamic range requirements of the input signal. This architecture has been successfully deployed in GSM/GPRS cellular receivers with the Silicon Laboratories Aero® receiver.
Real World Example – Si4700 FM tuner
The Si4700 is the industry’s first radio tuner IC to leverage a digital low-IF architecture and a 100 percent CMOS process technology, resulting in a completely integrated solution that requires only one external supply bypass capacitor and less than 20 mm2 of board space. Figure 7 shows a block diagram of the Si4700/01 FM tuner. This IC leverages Silicon Laboratories’ proven Aero digital low-IF receiver architecture and synthesizer technology to deliver superior RF performance and interference rejection. The digital low-IF architecture allows for the elimination of external components and factory adjustments due to analog process variations. This mixed-signal architecture allows digital signal processing (DSP) to perform channel selection, FM demodulation and stereo audio processing to achieve superior performance compared to traditional analog architectures.
Figure 7. Block Diagram of the Si4700/01 Digital-Low IF FM Tuner
The Si4700 FM tuner achieves a sensitivity level of 2.5 µV without using any external matching circuits. It also has excellent overload immunity with an IP3 of 108 dBµV and adjacent and alternate channel selectivities of 50 dB and 70 dB, respectively. DSP is utilized to provide optimum sound quality for varying signal reception conditions. This high level of integration, performance and interference rejection is directly attributable to the digital low-IF radio architecture and the digital implementation of the channel selection and FM demodulation functions. In addition to simplifying and reducing design time, the high integration of the digital low-IF architecture increases quality and improves manufacturability since external components are not required.
A new era for FM tuners has begun with the implementation of the digital low-IF receiver architecture into FM tuners. Digital architecture has revolutionized FM tuner design by enabling complete CMOS integration of the FM receiver onto an IC. The integration was achieved while offering excellent sensitivity and interference performance as demonstrated by Silicon Laboratories Si4700 FM tuner. Continued improvements in CMOS technology will also benefit digital low-IF FM tuners because all of the FM signal processing functions are implemented in the digital domain. Single-chip FM tuners can ease the adoption of FM tuners in nearly any portable consumer electronic device by simplifying the design process. A complete system on a chip also minimizes external bill-of-materials. In addition, designers can test and guarantee the complete system at the IC manufacturers test facility. This helps to improve the quality and manufacturability of the end product. Ultimately, consumer demand will drive the adoption of FM tuners into portable electronic devices, and the new digital low-IF FM tuners will continue to simplify design and manufacturability.
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