Designing Ultra Low Noise Amplifiers for Infrastructure Receiver Applications
Designing Ultra Low Noise Amplifiers for Infrastructure Receiver Applications
By Fikret Altunkilic, Alan Miller, Vivian Tzanakos and Michele Lewis/Skyworks
Amplifiers used in wireless infrastructure receiver applications have the key requirements of low noise, high linearity, and unconditional stability. In order to meet these needs, Skyworks has developed a new family of low noise amplifiers (LNAs) implemented in 0.5 μm enhancement mode (E-Mode) pHEMT. The SKY67101-396LF, covering 0.7–1.0 GHz, and the SKY67100-396LF, covering 1.7–2.0 GHz, are appropriate for application in GSM, WCDMA, TDSCDMA, and LTE infrastructure receiver chains. For low cost and efficient use of PCB space, the LNAs are housed in a 2 x 2 mm QFN package and share a common layout among the frequency bands.
Noise figure (NF) performance is a key parameter in receiver systems as it describes the capability for reception of low-level signals. The lower the noise figure, the better the receiver sensitivity. Linearity performance, represented as third order intercept (IP3), is also important as it indicates the ability to amplify signals with low intermodulation distortion from signals close in frequency. Unconditional stability is the ability for the amplifier to provide oscillation free performance under any input or output load conditions. Other specifications including current consumption, return loss, and human body model electro static discharge (HBM ESD) performance are also important and need to be taken into consideration in an LNA design. To obtain optimized performance with minimum trade-offs, special design techniques have been incorporated. Target specifications for low- and high-band LNAs are shown in Table 1.
Table 1. LNA Specifications at VDD = 5 V, Temp. = 25 °C
Technology and Topology Selection
A 0.5 μm enhancement mode pHEMT technology has been selected for excellent RF performance, superior low noise and high linearity. It also simplifies MMIC design by only requiring a positive voltage at the gate of FETs. This enables direct source connection to ground without requiring extra components for a self-bias structure. Very accurate models are available for circuit simulations.
A cascode LNA topology is used in the design because of its wide bandwidth, high gain and high-reverse isolation.
The design of the SKY67101-396LF 900 MHz LNA is detailed in this paper. The SKY67100-396LF 1900 MHz design was designed by a frequency scaling technique using the same methodology. Measured and simulated results of low and high bands are shown in the “Comparison of Measured and Simulated Results” section.
An active biasing circuit is shown in Figure 1 that stabilizes the current consumption of the LNA around approximately 55 mA over temperature, process, and supply voltage. R1 is used to set the voltage at pin 4 to set the total bias current. Any variation in supply bias is stabilized by the active bias circuitry. Stabilized gate voltage is fed to pin 2 through the L1 inductor. These components are also used for input impedance and noise figure source impedance matching.
Figure 1. Bias, Matching Components and Package
Measured vs. simulated supply current variation over temperature (-40 °C to +80 °C) is about 3 mA as shown in Figure 2.
Figure 2. Compensated Results of Measured vs. Simulated Current over Temperature
Noise Figure and Input Match
Noise figure and input return loss are the main factors in an LNA design. The first stage of the cascode design was designed for optimum noise figure, output impedance match, and P1dB at the target drain source current (Ids). The buffer stage was designed for optimal IP3 performance, output match, and P1dB while not degrading other performance specifications. The topology is made stable over almost all impedances by using source degeneration (it is made fully, unconditionally stable after adding an inter-stage network, output network, transmission line loss, and SMT component parasitic impedance. See “Linearity” and “Stability” sections). Figure 3 shows gain and NFmin (minimum noise figure) trade-off over frequency of the topology.
Figure 3. Gain vs. NFmin Trade-Off over Frequency
Figure 4 shows constant NF circles, source stability circle and available gain circles of the cascode topology in the source stable region of the Smith chart at 900 MHz.
Figure 4. Available Gain and Noise Circles
By considering the parasitic effects of SMT components and transmission line losses, a source impedance point of Zs = 64 + j44 ohms is selected in the 0.4 dB noise circle and 18 dB gain circle for the trades-off between noise, gain, and input return loss matching. The input matching network is realized by C1, C2, and L1. C1 and L1 are selected as high-Q components to achieve best NF. C1 is also used for DC blocking. Simulated gain, input return loss, and noise figure can be seen in the “Comparison of Simulated and Measured Results” section.
Linearity (OIP3) and P1 dB
Input and output terminations in band and out of band directly affect the linearity performance of the amplifier. The input and output loads of the amplifier can be swept directly through source and load pull technique. In this section, after the source is matched, the load-pull measurement is performed.
After the source is matched to an impedance of Zs = 64 + j44 ohms for desired NF, input return loss, and gain at the bias current, P1 dB and OIP3 are determined by the output matching and feedback network. Simulation models are used to estimate OIP3 at 0.9 GHz, for two tones separated by 5 MHz, with input power PIN = -20 dBm for each tone. Figure 5 shows load-pull impedances on the Smith chart and the circle shows the best OIP3 region at 0.9 GHz. Figure 6 shows OIP3 and delivered power contours at 0.9 GHz.
Figure 5. Simulated Load Pull for OIP3, Delivered Power and IMD3
Figure 6. OIP3 and Delivered Power Contours
Final load pull simulation and matching should be done after connecting input and output matching circuits as shown in Figure 1. After matching the source and load, simulated OIP3 and P1 dB results are shown in Figure 7 and Figure 8, respectively.
Figure 7. Simulated OIP3 After Source and Load Are Matched
Figure 8. Simulated P1 dB After Source and Load Are Matched
Stability is one of the most important requirements to consider for an LNA. Typical specifications dictate unconditionally stable operation up to 18 GHz. Each stage must be designed for unconditionally stable operation, including all the external components and biasing over all conditions. A very low-noise device with high gain usually becomes highly unstable in most of this frequency range. In order to stabilize the device and meet these requirements, multiple stability design techniques have been employed.
In order to solve stability problems at low to operating frequencies, usually some value of a source inductor is used. A source degeneration inductor used for input and noise-figure match can be used for stability purpose as well. One technique that is commonly used is to have a series-parallel LR network. This network behaves like low impedance at low frequencies and high impedance at higher frequencies.
Another technique that is commonly used is a shunt-series CR network connected from drain to ground. This network behaves like a shunt resistor at high frequencies and high impedance at low frequencies. A shunt resistor connected to ground helps to stabilize the device.
Another method that is used to improve stability is the shunt feedback between the output and the input of the device. However, this method degrades the noise figure. Therefore, it is not used in the first stage design but it is used in the second stage (buffer) design. This feedback also helps the IP3, return loss (RL) and gain adjustment.
Stabilizing circuits are integrated into the cascode LNAs. Final simulated stability and measured stability results of SKY67100 and SKY67101 are presented in Figures 16 and 17.
Electrostatic discharge (ESD) is the transfer of electrostatic charge between bodies or surfaces at different electrostatic potential and can be particularly destructive for semiconductors. ESD must be considered in the early phase of product development. Power clamps, diode, and stacked diodes ESD protection circuits are used in the design to achieve Class 1A (>250 V) HBM rating between all pin combinations. ESD protection circuits were used in different parts of the design, with careful attention paid to ensure that small-signal, large-signal, and noise figure performance were not degraded.
The SKY67100/SKY67101 application test board layout was designed to achieve the lowest possible noise figure and best stability performance. The test board was realized using 10-mils-thick Rogers 4350B substrate on 50-mils-thick FR4 supporting substrate. The Rogers 4350B material was selected for the RF circuit for its low dielectric constant (εr) and low εr variation over temperature for the best possible noise performance. The lower cost FR4 material is used to support remaining layers and provide added mechanical rigidity and thickness. Microstrip line widths and spacing were designed to accept commonly-used 0402 sized surface mount components while maintaining a uniform 50 ohm system. Copper thickness is 1.4 mils to reduce circuit losses and their additive effects on noise figure. The evaluation board is biased with a single 4.0 V power supply.
The test board schematic is shown in Figure 9. The input components C1, C2 and L1 determine the input match and noise figure of the device. For optimum noise figure to be achieved, it is recommended that high-Q components are used.
Figure 9. SKY67101-396LF Evaluation Board Layout
Components R2 and C4 comprise the feedback circuitry of the device if gain adjustment is needed.
The output match is realized through components L2 and C5. L2 is also used for decoupling at the bias line with components C6, C7 and C8. Linearity can be optimized by tuning the output match.
Comparison of Simulated and Measured Results
Figures 10 and 11 illustrate the measured and simulated gain profiles of SKY67100-396LF (1.9 GHz) and SKY67101-396LF (0.9 GHz) over a broadband frequency range. The gain for the SKY67101 is 18.2 dB at 0.9 GHz and the gain for SKY67100 is 17.67 dB at 1.9 GHz.
Figure 10. SKY67101 Simulated and Measured Gain
Figure 11. SKY67100 Simulated and Measured Gain
In Figure 12, the input and output return losses of the SKY67101 device are depicted. Both input and output return losses measure greater than 20 dB at 0.9 GHz.
Figure 12. SKY67101 Simulated and Measured Return Losses
Input and output return losses of the SKY67100 device are depicted in Figure 13.
Figure 13. SKY67100 Simulated and Measured Input and Output Return Loss
In-band OIP3 and P1dB performance are shown in Figures 14 and 15. OIP3 measurements were taken at 900 +/- 5 MHz for the SKY67101 and at 1950 +/- 5 MHz for the SKY67100.
Figure 14. SKY67101 Simulated and Measured Large Signal Data
Figure 15. SKY67100 Simulated and Measured Large Signal Data
Figures 16 and 17 exhibit the measured versus simulated NF performance for the SKY67101 and SKY67100 respectively. A correction factor of 0.05 dB was applied to account for losses due to the input connector and evaluation board transmission line to the first matching component for the SKY67101 and 0.1 dB was applied for the SKY67100.
Figure 16. SKY67101 Simulated and Measured Noise Figure (NF)
Figure 17. SKY67100 Simulated and Measured Noise Figure (NF)
Figures 18 and 19 illustrate the measured and simulated stability performance of the SKY67101 and SKY67100 respectively. Both devices exhibit unconditional stability over the broadband range as B > 0 and Rollet’s stability factor K > 1.
Figure 18. SKY67101 Simulated and Measured Stability
Figure 19. SKY67100 Simulated and Measured Stability
This paper has presented the design of a pair of low noise, high linearity amplifiers, SKY67100 and SKY67101. These LNAs are implemented using enhancement mode pHEMT devices in a cascode topology. The LNAs are appropriate for receiver applications in various wireless infrastructure products. They both utilize a common pinout and layout in a small, low cost 2 x 2 mm QFN package.
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